A Novel Design for Evaluating Simultaneous Switching Noise within an Enhanced IBIS Model

Simultaneous switching noise (SSN) is a major cause of power integrity (PI) degradation that causes circuits to become unstable and experience errors. As modern ICs operate at higher speeds with higher density and lower voltages, SSN has become a serious issue that must be addressed to ensure system stability during the short riseand fall-times of the logic transient states. Most traditional designs have generally used decoupling capacitors to reduce SSN. As these capacitors become equivalent series inductances when the system operates at high frequencies, such a technique works against reducing SSN. Therefore, we propose a methodology called the enhanced IBIS model that effectively alleviates the problem of SSN using an evaluation based on the enhanced I/O buffer information specification (IBIS) model with decoupling capacitors and a high-frequency lowimpendence circuit. In this study, we showed that SSN from 452 mV, 290 mV, 163 mV, and 301 mV, of IBIS, traditional decoupling capacitors, IBIS with a high-frequency low-impendence circuit, and HP Simulation Program with Integrated Circuit Emphasis (HSPICE) methodologies, respectively, was effectively reduced by 121 mV of our enhanced IBIS mode as measured by the peak-to-peak value. That is, our new method reduces noise by more than 73.2%, 58.3%, 25.7%, and 59.8% compared to other four methodologies, respectively. Key Word: Simultaneous Switching Noise (SSN), Power Integrity (PI), I/O Buffer Information Specification (IBIS), HSPICE, High-frequency low-impedance (HFLI) circuit.